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IESS 2007 -
Final Program |
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(last update: 05/22/07) |
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Download
as printer-friendly PDF: |
IESS2007_Program.pdf |
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Flyer version: |
IESS2007_Flyer.pdf |
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(a) Schedule |
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Time |
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Wednesday |
Thursday |
Friday |
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May 30, 2007 |
May 31, 2007 |
June 1, 2007 |
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7:30 AM |
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8:30 AM |
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Breakfast |
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8:30 AM |
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9:45 AM |
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Session 1 |
Session 5 |
Session 9 |
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Opening |
Opening |
Opening |
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Keynote 1 |
Keynote 2 |
Panel |
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9:45 AM |
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10:00 AM |
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Coffee Break |
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10:00 AM |
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12:00 PM |
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Session 2 |
Session
6 |
Session
10 |
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Validation and Verification |
Specification and Partitioning |
Network on Chip |
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12:00 PM |
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1:00 PM |
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Lunch Break |
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1:00 PM |
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3:10 PM |
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Session 3 |
Session 7 |
Session
11 |
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Automotive Applications |
Tutorial 1 |
Tutorial 2 |
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Design
Methodologies |
Medical Applications |
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3:10 PM |
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3:30 PM |
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Coffee Break |
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3:30 PM |
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5:30 PM |
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Session 4 |
Session
8 |
Session
12 |
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Hardware Synthesis |
Embedded Software |
Distributed and Network Systems |
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5:30 PM |
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6:00 PM |
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6:00 PM |
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10:00 PM |
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IFIP WG10.2 Meeting |
Social Event |
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Questions? |
Contact the Program Chair
Rainer Dömer (doemer@uci.edu) |
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(b) Sessions |
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Wednesday, May 30, 2007 |
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8:30 AM |
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9:45 AM |
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Session 1: Opening |
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Chair: Achim Rettberg (University of Paderborn,
Germany) |
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8:30 AM |
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8:45 AM |
1.1 |
Welcome to IESS 2007 |
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Achim Rettberg*, Mauro
Zanella**, Franz Rammig*, Rainer Dömer***, Andreas Gerstlauer*** |
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*University of Paderborn, Germany, **ZF
Lemförder GmbH, Germany, ***University of California, Irvine |
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8:45 AM |
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9:45 AM |
1.2 |
Where is System-Level Synthesis? |
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Keynote |
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Daniel D. Gajski |
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University of California, Irvine |
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10:00 AM |
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12:00 PM |
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Session 2: Validation and Verification |
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Chair: Samar Abdi (University of California,
Irvine) |
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10:00 AM |
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10:30 AM |
2.1 |
Requirements and Concepts for Transaction Level
Assertion Refinement |
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Best Paper Nominee |
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Wolfgang Ecker, Volkan
Esen, Thomas Steininger, Michael Velten |
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Infineon Technologies AG, Germany |
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10:30 AM |
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11:00 AM |
2.2 |
Using a Runtime Measurement Device with
Measurement-Based WCET Analysis |
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Bernhard Rieder,
Ingomar Wenzel, Klaus Steinhammer, Peter Puschner |
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Technical University of Wien, Austria |
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11:00 AM |
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11:20 AM |
2.3 |
Implementing Real-Time Algorithms by using the
AAA Prototyping Methodology |
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(s) |
Pierre Niang, Thierry
Grandpierre, Mohamed Akil |
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ESIEE Paris, France |
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11:20 AM |
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11:40 AM |
2.4 |
Run-Time efficient Feasibility Analysis of
Uni-Processor Systems with Static Priorities |
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(s) |
Karsten Albers, Frank
Bodmann, Frank Slomka |
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University of Ulm, Germany |
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11:40 AM |
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12:00 PM |
2.5 |
Approach for Formal Verification of a
Bit-serial Pipelined Architecture |
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(c) |
Henning Zabel, Achim Rettberg, Alexander Krupp |
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University of Paderborn, Germany |
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1:00 PM |
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2:50 PM |
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Session 3: Automotive Applications |
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Chair: Mauro Zanella (ZF Lemförder GmbH,
Germany) |
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1:00 PM |
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1:30 PM |
3.1 |
Automotive System Optimization using
Sensitivity Analysis |
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Best Paper Nominee |
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Razvan Racu, Arne
Hamann, Rolf Ernst |
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Technical University of Braunschweig, Germany |
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1:30 PM |
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2:00 PM |
3.2 |
Towards a Dynamically Reconfigurable Automotive
Control System Architecture |
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R.
Anthony*, A. Rettberg**, D. Chen***, I. Jahnich**, G. de Boer****, C.
Ekelin***** (presenter: T. Qureshi***) |
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*U. of
Greenwich, England, **U. of Paderborn, Germany, ***Royal Inst. of Tech.,
Sweden, ****Bosch, Germany, *****Volvo, Sweden |
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2:00 PM |
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2:30 PM |
3.3 |
An OSEK/VDX-based Multi-JVM for Automotive
Appliances |
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Christian Wawersich, Michael
Stilkerich, Wolfgang Schröder-Preikschat |
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University of Erlangen-Nuremberg, Germany |
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2:30 PM |
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2:50 PM |
3.4 |
Towards Dynamic Load Balancing for Distributed
Embedded Automotive Systems |
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(s) |
Isabell Jahnich, Achim
Rettberg |
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University of Paderborn, Germany |
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3:30 PM |
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5:30 PM |
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Session 4: Hardware Synthesis |
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Chair: Luigi Carro (Federal University of Rio
Grande do Sul, Brazil) |
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3:30 PM |
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4:00 PM |
4.1 |
Automatic Data Path Generation from C code for
Custom Processors |
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Best Paper Nominee |
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Jelena Trajkovic,
Daniel Gajski |
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University of California, Irvine |
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4:00 PM |
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4:30 PM |
4.2 |
Interconnect-aware Pipeline Synthesis for Array
based Reconfigurable Architectures |
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Shanghua Gao, Kenshu
Seto, Satoshi Komatsu, Masahiro Fujita |
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University of Tokyo, Japan |
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4:30 PM |
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4:50 PM |
4.3 |
An Interactive Design Environment for C-based
High-Level Synthesis |
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(s) |
Dongwan Shin, Andreas
Gerstlauer, Rainer Dömer, Daniel D. Gajski |
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University of California, Irvine |
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4:50 PM |
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5:10 PM |
4.4 |
Integrated
Coupling and Clock Frequency Assignment of Accelerators During
Hardware/Software Partitioning |
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(s) |
Scott Sirowy, Frank Vahid |
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University of California, Riverside |
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5:10 PM |
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5:30 PM |
4.5 |
Embedded Vertex Shader in FPGA |
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(c) |
Lars Middendorf, Felix Mühlbauer, Georg Umlauf,
Christophe Bobda (presenter: Klaus Drechsler) |
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University of Kaiserslautern, Germany |
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Thursday, May 31, 2007 |
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8:30 AM |
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9:45 AM |
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Session 5:
Opening |
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Chair: Rainer Dömer (University of California,
Irvine) |
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8:30 AM |
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8:45 AM |
5.1 |
Best Paper Awards |
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Best Paper Awards |
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Rainer Dömer*, Mike
Olivarez**, Flavio Wagner***, Hermann Kopetz**** |
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*Univ.
of California, Irvine, **Freescale Semiconductor, ***Fed. University
of Rio Grande do Sul, ****Vienna University of Technology |
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8:45 AM |
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9:45 AM |
5.2 |
Fine Granular Configurable RTOS for Ultra-low Resource Devices |
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Keynote |
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Franz Rammig |
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University of Paderborn, Germany |
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10:00 AM |
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12:00 PM |
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Session 6: Specification and Partitioning |
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Chair: Jianwen Zhu (University of Toronto,
Canada) |
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10:00 AM |
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10:30 AM |
6.1 |
A Hybrid Approach for System-Level Design
Evaluation |
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Alexander Viehl*,
Markus Schwarz*, Oliver Bringmann*, Wolfgang Rosenstiel** |
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*FZI Forschungszentrum Informatik, Germany,
**University of Tübingen, Germany |
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10:30 AM |
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11:00 AM |
6.2 |
Automatic Parallelization of Sequential
Specifications for Symmetric MPSoCs |
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Fabrizio Ferrandi, Luca Fossati, Marco
Lattuada, Gianluca Palermo, Donatella Sciuto, Antonino
Tumeo |
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Politecnico di Milano, Italy |
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11:00 AM |
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11:30 AM |
6.3 |
An Interactive Model Re-Coder for Efficient SoC
Specification |
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Pramod Chandraiah,
Rainer Dömer |
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University of California, Irvine |
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11:30 AM |
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12:00 PM |
6.4 |
Constrained
and Unconstrained Hardware-Software Partitioning using Particle Swarm
Optimization Technique |
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M. B. Abdelhalim, A. E.
Salama, S. E.-D. Habib |
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Cairo University, Egypt |
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1:00 PM |
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3:10 PM |
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Session 7: Design Methodologies |
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Chair: Andreas Gerstlauer (University of
California, Irvine) |
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1:00 PM |
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2:30 PM |
7.1 |
Embedded SW Design Space Exploration and
Automation using UML-Based Tools |
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Tutorial |
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Flavio R. Wagner, Luigi Carro |
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Federal University of Rio Grande do Sul,
Brazil |
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2:30 PM |
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2:50 PM |
7.2 |
Using
Aspect-Oriented Concepts in the Requirements Analysis of Distributed
Real-Time Embedded Systems |
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(s) |
Edison
P. Freitas*, Marco A. Wehrmeister**, Carlos E. Pereira*, Flavio R. Wagner*, Elias T. Silva
Jr*, Fabiano C. Carvalho* |
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*Universidade Federal do Rio Grande do Sul,
Brazil, **University of Paderborn, Germany |
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2:50 PM |
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3:10 PM |
7.3 |
Smart Speed TechnologyTM |
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(c) |
Mike Olivarez, Brian Beasley |
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Freescale Semiconductor, USA |
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3:30 PM |
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5:30 PM |
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Session 8: Embedded Software |
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Chair: Flavio R. Wagner (Federal University of
Rio Grande do Sul, Brazil) |
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3:30 PM |
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4:00 PM |
8.1 |
Power
Optimization for Embedded System Idle Time in the Presence of Periodic
Interrupt Services |
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Gang Zeng, Hiroyuki
Tomiyama, Hiroaki Takada |
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Nagoya University, Japan |
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4:00 PM |
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4:30 PM |
8.2 |
Reducing the Code Size of Retimed Software
Loops under Timing and Resource Constraints |
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Noureddine Chabini*,
Wayne Wolf** |
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*Royal Military College of Canada, **Princeton
University |
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4:30 PM |
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4:50 PM |
8.3 |
Identification
and Removal of Program Slice Criteria for Code Size Reduction in Embedded
Systems |
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(s) |
Mark Panahi, Trevor
Harmon, Juan A. Colmenares, Shruti Gorappa,
Raymond Klefstad |
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University of California, Irvine |
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4:50 PM |
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5:10 PM |
8.4 |
Configurable Hybridkernel for Embedded
Real-Time Systems |
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(s) |
Timo Kerstan, Simon
Oberthür |
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University of Paderborn, Germany |
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5:10 PM |
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5:30 PM |
8.5 |
Embedded Software Development in a System-Level
Design Flow |
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(c) |
Gunar Schirner, Gautam
Sachdeva, Andreas Gerstlauer, Rainer Dömer |
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University of California, Irvine |
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Friday, June 01, 2007 |
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8:30 AM |
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9:45 AM |
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Session 9: Opening |
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Chair: Franz Rammig (University of Paderborn,
Germany) |
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8:30 AM |
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8:45 AM |
9.1 |
Announcement of IESS 2009 |
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Franz Rammig |
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University of Paderborn, Germany |
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8:45 AM |
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9:45 AM |
9.2 |
Modeling of Software-Hardware Complexes |
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Panel |
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K.H. (Kane) Kim*, Wayne Wolf**, Nikil Dutt*, Hermann Kopetz***, Franz J. Rammig**** |
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*University
of California, Irvine, **Princeton University, ***Vienna University of
Technology, ****University of Paderborn |
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10:00 AM |
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12:00 PM |
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Session 10: Network on Chip |
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Chair: Hiroyuki Tomiyama (Nagoya University,
Japan) |
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10:00 AM |
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10:30 AM |
10.1 |
Data Reuse Driven Memory and Network-On-Chip
Co-Synthesis |
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Ilya Issenin, Nikil Dutt |
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University of California, Irvine |
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10:30 AM |
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11:00 AM |
10.2 |
Efficient
and Extensible Transaction Level Modeling Based on an Object Oriented Model
of Bus Transactions |
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Rauf Salimi Khaligh, Martin
Radetzki |
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University of Stuttgart, Germany |
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11:00 AM |
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11:30 AM |
10.3 |
Hardware Implementation of the Time-Triggered
Ethernet Controller |
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Klaus Steinhammer,
Astrit Ademaj |
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Vienna University of Technology, Austria |
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11:30 AM |
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12:00 PM |
10.4 |
Error Containment in the Time-Triggered
System-On-a-Chip Architecture |
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R. Obermaisser, H.
Kopetz, C. El Salloum, B. Huber |
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Vienna University of Technology, Austria |
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1:00 PM |
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3:10 PM |
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Session 11: Medical Applications |
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Chair: Mike Olivarez (Freescale Semiconductor, USA) |
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1:00 PM |
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2:30 PM |
11.1 |
Medical Embedded Systems |
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Tutorial |
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Roozbeh Jafari*, Soheil
Ghiasi**, Majid Sarrafzadeh*** |
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*University of Texas at Dallas, **University
of California, Davis, ***University of California, Los Angeles |
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2:30 PM |
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2:50 PM |
11.2 |
Generic Architecture Designed for Biomedical
Embedded Systems |
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(s) |
L. Sousa, M. Piedade, J.
Germano, T. Almeida, P. Lopes, F. Cardoso, P.
Freitas |
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Technical University of Lisbon, Portugal |
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2:50 PM |
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3:10 PM |
11.3 |
A Small
High Performance Microprocessor Core Sirius for Embedded Low Power Designs,
Demonstrated in a Medical Mass Application of an
Electronic Pill (EPille®) |
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(c) |
Dirk Jansen, Nidal Fawaz, Daniel Bau, Marc Durrenberger |
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University of Applied Sciences, Offenburg,
Germany |
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3:30 PM |
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5:10 PM |
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Session 12: Distributed and Network Systems |
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Chair: Carlos E. Pereira (Federal University of
Rio Grande do Sul, Brazil) |
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3:30 PM |
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4:00 PM |
12.1 |
Utilizing Reconfigurable Hardware to optimize
Workflows in Networked Nodes |
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Dominik Murr*, Felix Mühlbauer*, Falko
Dressler**, Christophe Bobda* (presenter: Klaus
Drechsler*) |
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*Kaiserslautern University of Technology,
Germany, **University of Erlangen-Nuremberg, Germany |
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4:00 PM |
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4:30 PM |
12.2 |
Dynamic Software Update of Resource-Constrained
Distributed Embedded Systems |
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Meik Felser, Rüdiger
Kapitza, Jürgen Kleinöder, Wolfgang Schröder-Preikschat |
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University of Erlangen-Nuremberg, Germany |
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4:30 PM |
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4:50 PM |
12.3 |
Configurable Medium Access Control for Wireless
Sensor Networks |
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(s) |
Lucas F. Wanner, Augusto B. de Oliveira, Antônio A. Fröhlich |
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Federal University of Santa Catarina, Brazil |
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4:50 PM |
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5:10 PM |
12.4 |
Integrating Wireless Sensor Networks and the
Grid through POP-C++ |
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(c) |
Augusto B. de Oliveira*, Lucas F. Wanner*,
Pierre Kuonen**, Antônio A. Fröhlich* |
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*Federal University of Santa Catarina, Brazil,
**University of Applied Sciences of Fribourg, Switzerland |
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Legend: |
(s) = Short paper |
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(c) = Case study |
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underlined = Speaker |
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Questions? |
Contact the Program Chair
Rainer Dömer (doemer@uci.edu) |
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(last update: 05/22/07) |
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(c) Program
Highlights |
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Keynote Addresses |
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Wednesday, May 30,
2007 |
Where is
System-Level Synthesis? |
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8:45 AM |
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9:45 AM |
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Daniel D. Gajski |
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University of California, Irvine |
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Abstract: |
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With complexities of multi-core Systems-on-Chip (SOCs) rising
almost daily, the design community has been searching for a new methodology
that can handle given complexities with increased productivity and decreased
time-to-market. The obvious solution that comes to mind is increasing levels
of abstraction, or in other words, increasing the size of the basic building
blocks. However, it is not clear what these basic blocks should be and what
should be the strategy for composing a system design out of these basic
blocks. To make things more difficult, the difference between software and
hardware is becoming indistinguishable which, in turn, requires sizable
change in the industrial and academic infrastructure. |
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In
order to find the solution, we will look first at the system gap between SW
and HW designs and derive requirements for the system design flow that
includes software as well as hardware. In order to enable new tools for model
generation, simulation, synthesis and verification, the design flow has to be
supported by well defined abstraction levels, model semantics and
transformations that correspond to design decisions made by designers. In
order to satisfy those requirements we need some formalization of the design
process. For this purpose, we will introduce the concept of model algebra
that can serve as an enabler for the new strategy in system design and,
consequently, system industry. Furthermore, we will demonstrate our approach
on MP3 design and show increased simplicity and huge productivity gains for
complex systems. We will explain the benefits and finish with a prediction
and a roadmap toward the final goal of increasing productivity by several
orders of magnitude while reducing expertise level needed for design of
billion-transistor systems to the basic principles of design science only. |
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Thursday, May 31,
2007 |
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Fine Granular Configurable RTOS for Ultra-low Resource Devices |
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8:45 AM |
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9:45 AM |
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Franz Rammig |
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University of Paderborn, Germany |
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Abstract: |
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When designing a kernel for an operating system the developer
has to choose between an microkernel or monolithic kernel approach. Bases for
the decision is mostly the tradeoff between security and performance.
Depending on application demands and on the available hardware a microkernel
or a monolithic kernel approach or something between is desired. In this
paper we present a hybrid kernel for embedded real-time systems which can be
configured to the application demands in an easy way. To realize the hybrid
kernel we present a technique to guarantee memory access in O(1) with virtual
memory. With our approach the same codebase can be used for system services
to be placed either in userspace or in kernelspace. |
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Panel Discussion |
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Friday, June 01,
2007 |
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Modeling
of Software-Hardware Complexes |
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8:45 AM |
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9:45 AM |
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K.H. (Kane) Kim |
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University of California, Irvine |
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Abstract: |
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Various issues related to modeling of software-hardware
complexes, including the following, will be addressed. |
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Are those currently available modeling approaches insufficient
for use in systematic design and optimization of embedded software and
hardware systems? |
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Are there potential synergies between software modeling and
hardware modeling approaches? |
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What are the possibilities of and obstacles in combining some
software modeling approaches and some hardware modeling approaches? |
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What are the kinds of things that software-modeling experts wish
to learn from the work on hardware modeling? |
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Panelists: |
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Nikil Dutt, University of California,
Irvine |
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Hermann Kopetz, Vienna University of
Technology, Austria |
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Franz Rammig, University of Paderborn,
Germany |
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Wayne Wolf, Princeton University |
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Kane Kim, University of California,
Irvine |
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Tutorials |
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Thursday, May 31,
2007 |
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Embedded
SW Design Space Exploration and Automation using UML-Based Tools |
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1:00 PM |
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2:30 PM |
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Flavio R. Wagner, Luigi Carro |
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Federal University of Rio Grande
do Sul, Brazil |
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Abstract: |
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This tutorial discusses design space exploration and software
automation based on an UML front-end. First, we review software automation
tools targeted at the embedded systems domain. Following, we present an
approach for the estimation of memory, performance, and energy of a given
application modeled from an initial UML specification. We proceed with an
analysis of the possibilities of linking different modeling environments for
software generation (Simulink and UML, for example). Finally, we show the possibilities
of using other specification languages to obtain more abstraction and allow
design space exploration together with software automation. |
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Friday, June 01,
2007 |
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Medical
Embedded Systems |
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1:00 PM |
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2:30 PM |
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Roozbeh Jafari*, Soheil
Ghiasi**, Majid Sarrafzadeh*** |
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*University of Texas at Dallas,
**University of California, Davis, ***University of California, Los Angeles |
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Abstract: |
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Light-weight embedded systems for medical monitoring are often
referred to low-profile, small size, unobtrusive and potable processing
elements with limited power resources. Such systems typically incorporate
sensing, processing and communications and are often manufactured to be
simple and cost-effective. Being low profile and wearable immediately implies
the limitations in computational capabilities, memory (storage), speed and
I/O interfaces. In this tutorial, we portray a brief description of low-power
and light-weight embedded systems; present two pilot applications; and
illustrate their corresponding design challenges. We specifically discuss the
reconfiguration techniques. |
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Best Paper Awards |
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Thursday, May 31,
2007 |
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Best Paper Awards |
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8:30 AM |
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8:45 AM |
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Rainer Dömer*, Mike
Olivarez**, Flavio Wagner***, Hermann Kopetz**** |
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*Univ. of California, Irvine, **Freescale Semiconductor,
***Fed. University of Rio Grande do Sul, ****Vienna University of Technology |
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Committee: |
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Mike Olivarez (Freescale Semiconductor, USA) |
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Flavio Wagner (Federal University of Rio Grande do Sul, Brazil) |
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Hermann Kopetz (Vienna University of Technology, Austria) |
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Nominees: |
2.1 |
Requirements and Concepts for Transaction Level
Assertion Refinement |
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Wolfgang Ecker, Volkan Esen, Thomas Steininger,
Michael Velten |
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Infineon Technologies AG, Germany |
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3.1 |
Automotive System Optimization using Sensitivity
Analysis |
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Razvan Racu, Arne Hamann, Rolf Ernst |
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Technical University of Braunschweig, Germany |
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4.1 |
Automatic Data Path Generation from C code for
Custom Processors |
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Jelena Trajkovic, Daniel Gajski |
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University of California, Irvine |
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Selection: |
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The top three papers with the highest overall review score
determined in the paper review process by the IESS Program Committee are
nominated for the Best Paper Award. These papers are being presented at the
first day of the conference. |
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The Best Paper Award Committee, composed of three members of the
Program Committee, selects the order among the nominees and thus determines
the winner of the Best Paper Award. The selection criteria are based on the
quality of the presentation and the technical contribution of the paper. |
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The Best Paper Award will be announced in the opening session at
the second day of the conference. |
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Social Event |
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Thursday, May 31,
2007 |
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IESS Party |
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6:00 PM |
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10:00 PM |
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Las
Brisas Restaurant |
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361 Cliff Drive |
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Laguna Beach,
CA 92651 |
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Location: |
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The IESS party will be held on the outdoor patio of the Las
Brisas restaurant providing seating and standing in a comfortable atmosphere.
The restaurant is nestled in a scenic location on top of the cliffs of Laguna
Beach, with walking access to the Pacific ocean and beaches. The menu will
feature a buffet of items inspired by the cuisine of the Californian and
Mexican Rivieras. |
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Admission: |
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All conference attendees and their guests are invited to attend
in oder to mingle and exchange with their friends and colleagues in a relaxed
environment. Admission to the event will be with ticket only. One ticket is
provided as part of each full conference registration. Additional tickets to
the event can be purchased for $80 each. |
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Transportation: |
A shuttle bus will be available to provide transportation of
conference attendees and their guests from the conference center and
conference hotels to the Las Brisas restaurant and back. The shuttle bus will
leave the conference center at approx. 6:00 PM and it will stop at the Atrium
and Radisson hotels (appr 6:15-6:30 PM) for pickup before continuing on to
the restaurant. On the return, the bus will pickup guests from Las Brisas at
10:00-10:15 PM for dropoff at the hotels or the conference center. |
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IFIP Meeting |
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Wednesday, May 30,
2007 |
IFIP WG10.2 Meeting |
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6:00 PM |
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8:00 PM |
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Balboa Room |
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(by invitation only) |
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The Working Group 10.2 (Embedded Systems, chaired by Wayne Wolf) of the
International Federation for Information Processing (IFIP), who organizes the
IESS Conference, will hold a meeting at the conference site. This meeting is
for members and by invitation only. |
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